The present disclosure relates generally to protecting circuits and their components from current surges. More specifically, the present disclosure relates to a bidirectional current limiter that limits both inrush and discharge currents.
The overall effectiveness of an electronic circuit depends on a variety of performance-related factors such as hold-up time during a power interruption, inrush current and discharge current.
The phrase “hold-up time” refers to the total amount of time, often measured in milliseconds, that a circuit can maintain operation within the specified voltage range after a loss of input power. Many “high-reliability” systems (e.g., aerospace systems) require that certain critical circuits or modules maintain operation during short term input-power interruptions. Input-power interruptions may be caused by a short-circuit of the input power wires, or by a switchover from a primary power source to a redundant power source when a power bus failure occurs. One method of maintaining circuit operation during a power interruption is to provide the circuit with bulk capacitive loads, which store energy that can be accessed and utilized during the power interruption.
Inrush current is the maximum instantaneous input current drawn by an electrical circuit when power is first applied to it. For example, when power is initially applied to a load circuit, a large inrush current flows that exceeds a steady-state current value of the load circuit and its components. When the load circuit includes a large capacitance, which may be required to meet a desired current hold-up time, during the initial application of power a large current flows into the load circuit to charge the capacitors. Additionally, immediately after power is turned on, other non-capacitive load circuit components can have low resistance, which also causes large current flows. As the load circuit components begin to generate heat and warm up, their resistance increases and the current drops to the steady-state current.
When the power applied to a load circuit is abruptly changed, for example, by a short circuit between the power input wires, a low resistance connection can occur between the power input wires. This results in excessive discharge current surges flowing out of the circuit's capacitive loads, which are greater than required to meet the circuit's desired hold-up time. The excess discharge current can damage upstream circuitry by producing very high temperatures due to the excessive power dissipation in the circuit. If the capacitive load is fully charged and high-voltage, the size of the resulting discharge current and power dissipation could cause significant damage to upstream circuit components.
To illustrate the concept of inrush current, FIG. 1 depicts an example of a current waveform that may occur when power is applied to a load circuit. When the power is turned on, current begins to flow until it reaches the peak current value, which is larger than the steady-state current value. The current value then gradually decreases until it stabilizes at the steady-state current. The shaded portion of the waveform that is prior to when the current reaches the steady-state is the inrush current. If the size of the inrush current exceeds what is allowed by the load circuit or its component parts, depending on the magnitude of the inrush current (i.e., the difference between the peak current value and the steady-state current value) and its duration (i.e., the pulse width), the load circuit and/or its component part(s) may overheat, potentially causing the load circuit and/or its component parts to malfunction or break down. A diagram similar to FIG. 1 may be generated for discharge current, which occurs further along the time axis (i.e., “x” axis) in the positive direction, and is a mirror image of the inrush current. Accordingly, the discharge current flows in the negative or opposite direction along the current axis (i.e., “y” axis).
As noted above, the overall effectiveness of a circuit depends on a variety of performance-related factors such as hold-up time during a power interruption, inrush current and discharge current. When hold-up time is addressed by, inter alia, providing a relatively large capacitive load in the circuit, the potential for inrush currents and discharge currents is even greater. It is desirable to provide a simple and efficient circuit configuration that delivers desired capacitor-based hold-up times, inrush current limits and/or discharge current limits.